1. Field of the Invention
The present invention relates to a hybrid integrated circuit containing an FPGA portion and an ASIC portion. More particularly, this invention relates to an interface between the FPGA and the ASIC portions of a hybrid integrated circuit.
2. The Prior Art
A field programmable gate array (FPGA) may be programmed to execute a wide variety of logic functions, providing designers the ability to design circuits for specific applications. Other advantages of an FPGA are that the design time is short so it can be marketed much quicker and the design is such that can be changed easily. In an FPGA, however, many of the gates may go unused. An application-specific integrated circuit (ASIC), on the other hand, is designed only to perform certain specific tasks, and therefore does not result in wasted gates. However the design and testing phase of an ASIC is quite complex and expensive because an ASIC must be mask-programmed, and therefore the production of an ASIC only makes fiscal sense when the ASIC is to be produced in large quantities.
A hybrid integrated circuit (IC) provides some portion of the advantages of both designs. A hybrid IC includes both an FPGA and an ASIC portion. Of major concern in designing a hybrid IC is providing a suitable interface between the FPGA and ASIC portions of the IC. In order for the IC to perform its tasks properly, the FPGA and ASIC portions must be able to communicate effectively with each other. Conventionally, the interface has been designed to have the ASIC portion communicate with the FPGA portion, as will be described below, through the boundary between the FPGA portion and the ASIC portion using a plurality of connections between the edge of the ASIC portion and the edge of the FPGA portion.
FIGS. 1A-1F depict several examples of different designs of the layout architecture of a hybrid IC as known in the art. In FIGS. 1A-1F, each IC 2 has a plurality of I/O modules 10 running along the perimeter of the IC 2 wherein the orientation of the FPGA portion 14 and the ASIC portion 2 varies among the figures.
FIG. 1A illustrates a smaller ASIC portion 12 positioned below a larger FPGA portion 14. FIG. 1B illustrates a larger ASIC 12 portion positioned below a smaller FPGA 14 portion. FIG. 1C illustrates an ASIC portion 12 positioned at the bottom right corner of an FPGA portion 14. FIG. 1D illustrates an ASIC portion 12 positioned at the upper left corner of and FPGA portion 14. FIG. 1E illustrates an ASIC portion 12 positioned within an FPGA portion 14, near the bottom right corner. FIG. 1F illustrates an FPGA portion 14 positioned within an ASIC portion 12, near the upper left corner. It will be appreciated that other orientations of the FPGA portion 14 and the ASIC portion 12 of the IC 2 are well known in the art.
In FIG. 2, the FPGA portion 14 and the ASIC portion 12 of the IC 2 depicted in FIG. 1A are illustrated in greater detail. In FIG. 2, the FPGA portion 14 is made up of an array of logic modules 16 with horizontal and vertical routing resources provided for connecting the logic modules 16 as well as for communication with the ASIC portion 12. Communication between the ASIC portion 12 and the FPGA portion 14 is then accomplished by connecting the ASIC portion 12 to the boundary between the FPGA portion 14 and the ASIC portion 12. The boundary between the FPGA portion 14 and the ASIC portion 12 is connected to the vertical or horizontal routing resources. Signals are then sent from the ASIC portion 12 through the boundary between the ASIC portion 12 and the FPGA portion 14 and through the horizontal and vertical routing resources until reaching the desired logic modules 16. Communication from the logic modules 16 of the FPGA portion 14 to the ASIC portion 12 is accomplished in the reverse manner by sending signals from the desired logic modules 16 through the horizontal and vertical routing resources of the FPGA portion 14 until reaching the boundary between the FPGA portion 14 and the ASIC portion 12 and into the ASIC portion 12.
FIG. 3 depicts another embodiment of a hybrid IC as known in the art. This embodiment contains an FPGA portion 14 having a multi-level hierarchial design (in this example, a three-level hierarchial design) rather than simply an array of logic modules. The FPGA portion 14 comprises nine logic blocks 18 having horizontal and vertical routing resources. Each logic block 18 comprises another nine logic blocks 20 having local routing resources. The logic blocks in the second level of the hierarchial design will be termed clusters in this specification to distinguish them from the logic blocks in the first level of the hierarchial design. It should be appreciated, however, that since such a hierarchial design may conceivably have an unlimited number of levels, each having logic blocks and local routing resources, the term “cluster” should not be read as limiting the invention to only a three-level design. Each of the logic blocks (clusters) 20 then comprises a plurality of logic blocks, which in this example are logic modules with local routing resources, but may also be configurable function generators, logic blocks containing another level of logic blocks, etc.
Communication between the ASIC portion 12 and the FPGA portion 14 is accomplished by connecting the ASIC portion 12 to the boundary between the FPGA portion 14 and the ASIC portion 12 and the first level of horizontal or vertical routing resources to the boundary between the FPGA portion 14 and the ASIC portion 12. Signals are then sent from the ASIC portion 12 through the boundary between the FPGA portion 14 and the ASIC portion 12 and through the horizontal and vertical routing resources at the first hierarchial level (the routing resources positioned between each logic block 18). The signals then pass to the horizontal and vertical routing resources at the second hierarchial level (the routing resources between each logic block or cluster 20) and then the third hierarchial level (the routing resources between each logic block at this level).
The interfaces described have several drawbacks. First, these interfaces run at relatively slow speeds. This slow speed is exasperated by the relatively large distances between the logic modules and the interface. Second, routing congestion is common at the boundary between the FPGA portion 14 and the ASIC portion 12 in these types of designs. Alleviating this routing congestion using a routing resource requires that a significant amount of space be allocated for the routing resource between the FPGA portion 14 and the ASIC portion 12.
In addition to the routing and speed problems of the prior art interfaces, the fixed pin location and order for signals sent from the ASIC 12 portion to the FPGA 14 portion may cause FPGA place and route difficulties. Also, the asymmetrical number of I/O connections required for each side of the FPGA portion may also cause FPGA place and route difficulties.
Another drawback of these interfaces is that they require that both the FPGA portion 14 and the ASIC 12 portion be hardwired onto the IC 2 during the design phase. This prevents the use of interchangeable modules for the FPGA portion 14 and the ASIC portion 12.
Clearly, an interface between the FPGA and ASIC portions of a hybrid IC that does not suffer from the drawbacks of the prior art is needed.